In electronic devices equipped with computing functionality, the ability of the device to process data is typically determined based on the capabilities of the processor. This may include, for example, the number of processing cores in the processor, the speed of each processing core, the size and/or speed of the processor memory cache, etc. In general, this method of prediction may be reliable when considering standalone computing devices. However, the data processing performance of an individual system may not be as influential to performance in a larger system that may comprise a large number of computing devices such as, for example, a data center that comprises a plurality of networked data servers, a cloud architecture comprising data processors, servers, etc. (e.g., providing software-as-a-service), high performance computing (HPC) systems, etc. For example, an HPC system may comprise individual computing devices (e.g., nodes) that may be organized into groups (e.g., clusters) to collaboratively process data. A master node in a cluster may break data processing jobs into smaller tasks for processing by compute nodes in the cluster. These operations may substantially parallelize data processing to generate faster results.
While the advantages may be apparent, grouping computing devices together to operate within a larger system may introduce a new set of performance issues. In addition to the ability of each individual computing device, the manner in which the computing devices interact must be considered. While organized in the same logical group, the physical location of devices may be within the same housing (e.g., in the same server case), in a rack separated by other nodes, in different racks, in different rooms, etc. The variability in relative location may present problems when data rates are limited due to loss induced by relatively long channel lengths (e.g., due to a large printed circuit board (PCB), long cable, etc.). When designing computing devices and the equipment employed to interconnect the computing devices in large systems, anticipating what the actual physical organization of the computing devices will be may be difficult given the variety of potential configurations that may be employed when implementing a large system.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications and variations thereof will be apparent to those skilled in the art.